When a semiconductor device, such as a metal-oxide-semiconductor field effect transistor (MOSFET) or a MOS capacitor, is scaled down through various technology nodes, a high dielectric constant κ (high-κ) dielectric (as compared to silicon dioxide) and a conductive material are used to form a gate structure. In the gate structure, an interfacial layer is used to improve an interface between a surface of a substrate and the high-κ dielectric for reducing damage and defects. The interfacial layer is further configured to suppress a mobility degradation of channel carriers in the semiconductor device and to help improve stability of device performance.